SH7047 Datasheet, PDF (655/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

In this example, the HSTBY pin is driven low, then the transition to hardware standby mode is
made. Hardware standby mode is cleared when the HSTBY pin is driven high and then the RES
pin is driven high after the elapse of the oscillation stabilization time of the clock pulse.
Oscillator
RES
HSTBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 24.3 Transition Timing to Hardware Standby Mode
24.3.4 Module Standby Mode
Module standby mode can be set for individual on-chip peripheral functions.
When the corresponding MSTP bit in MSTCR is set to 1, module operation stops at the end of the
bus cycle and a transition is made to module standby mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module standby mode is cleared and the
module starts operating at the end of the bus cycle. In module standby mode, the internal states of
modules are initialized.
After reset clearing, the SCI, MTU, MMT, CMT, and A/D converter are in module standby mode.
When an on-chip supporting module is in module standby mode, read/write access to its registers
is disabled.
24.4 Usage Notes
24.4.1 I/O Port Status
When a transition is mode to software standby mode while the port high-impedance bit (HIZ) in
SBYCR is 0, I/O port states are retained. Therefore, there is no reduction in current consumption
for the output current when a high-level signal is output.
Rev. 2.00, 09/04, page 615 of 720