SH7047 Datasheet, PDF (474/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.3.10 Transmit Acknowledge Registers (TXACK1, TXACK0)
TXACK1 and TXACK0 are 16-bit registers containing status flags that indicate normal
transmission of mailbox transmit messages.
• TXACK1
Bit Bit Name
15 TXACK31
14 TXACK30
13 TXACK29
12 TXACK28
11 TXACK27
10 TXACK26
9
TXACK25
8
TXACK24
7
TXACK23
6
TXACK22
5
TXACK21
4
TXACK20
3
TXACK19
2
TXACK18
1
TXACK17
0
TXACK16
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Status flags that indicate error-free transmission of
the transmit message in the corresponding
mailboxes from 16 to 31. When the message in
mailbox n (n = 16 to 31) has been transmitted error-
free, TXACKn is set to 1.
[Setting condition]
• Completion of message transmission for
corresponding mailbox
[Clearing condition]
• Writing 1
Notes: 1. Writing operation by the CPU is valid only
for clearing condition (writing 1) of set
status.
2. Restrictions apply to the use of the
mailbox 31 for transmission. Carefully
read section 15.8, Usage Notes.
Rev. 2.00, 09/04, page 434 of 720