SH7047 Datasheet, PDF (444/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

14.5.2 Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter
write has priority, so no increment occurs. Figure 14.7 shows the timing.
CMCNT write cycle
T1 T2
Pφ
Address
CMCNT
Internal write
signal
CMCNT
input clock
CMCNT
N
M
CMCNT write data
Figure 14.7 CMCNT Word Write and Increment Contention
Rev. 2.00, 09/04, page 404 of 720