SH7047 Datasheet, PDF (576/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

17.2 Precautions for Use
1. In this LSI series, individual functions are available as multiplexed functions on multiple pins.
This approach is intended to increase the number of selectable pin functions and to allow the
easier design of boards.
When the pin function controller (PFC) is used to select a function, only a single pin can be
specified for each function. If one function is specified for two or more pins, the function will
not work properly.
2. To select a pin function, set the port control registers (PACRL3, PACRL2, PACRL1, PBCR1,
PBCR2, PDCRL1, and PDCRL2) before setting the port I/O registers (PAIORL, PBIOR, and
PDIOR). To select the function of the pin which is multiplexed with the port E, the order of
setting the port control registers (PECRH, PECRL1, and PECRL2) and port I/O registers
(PEIORH and PEIORL) is not matter.
3. When external spaces are used, set the data input/output pins as follows by the pin function
controller (PFC), according to the bus size of the CS0 space specified by the bus control
register 1 (BCR1) of the bus state controller.
When the CS space takes the byte (8 bits) size, set all pins D7 to D0 as data input/output pins.
4. Regarding the pin in which input/output port is multiplexed with DREQ or IRQ, when the port
input is changed from low level to DREQ edge or IRQ edge detection mode, the corresponding
edge is detected.
5. In a state where the pin is in general I/O mode and set to 1-output (specifically, the port control
register is in general I/O mode and both the port I/O register and the port data register are set to
1), a power-on reset through the RES pin may generate a low level on this pin upon the power-
on state is realized. To prevent this low level from happening, set the port I/O register to 0
(general output) and then apply the power-on reset. Note, however, that no low level may be
generated internally by the power-on reset due to the WDT overflow.
Rev. 2.00, 09/04, page 536 of 720