SH7047 Datasheet, PDF (33/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Figure 25.7 Interrupt Signal Input Timing.................................................................................. 628
Figure 25.8 Interrupt Signal Output Timing ............................................................................... 628
Figure 25.9 Bus Release Timing................................................................................................. 628
Figure 25.10 Basic Cycle (No Waits) ......................................................................................... 630
Figure 25.11 Basic Cycle (One Software Wait) ......................................................................... 631
Figure 25.12 Basic Cycle (Two Software Waits + Waits by WAIT Signal) .............................. 632
Figure 25.13 MTU Input/Output timing ..................................................................................... 633
Figure 25.14 MTU Clock Input Timing ..................................................................................... 633
Figure 25.15 I/O Port Input/Output timing ................................................................................. 634
Figure 25.16 WDT Timing ......................................................................................................... 635
Figure 25.17 SCI Input Timing................................................................................................... 636
Figure 25.18 SCI Input/Output Timing ...................................................................................... 637
Figure 25.19 MMT Input/Output Timing ................................................................................... 638
Figure 25.20 POE Input/Output Timing ..................................................................................... 639
Figure 25.21 HCAN2 Input/Output timing................................................................................. 640
Figure 25.22 External Trigger Input Timing .............................................................................. 641
Figure 25.23 H-UDI Clock Timing ............................................................................................ 642
Figure 25.24 H-UDI TRST Timing ............................................................................................ 643
Figure 25.25 H-UDI Input/Output Timing ................................................................................. 643
Figure 25.26 AUD Reset Timing................................................................................................ 645
Figure 25.27 Branch Trace Timing............................................................................................. 645
Figure 25.28 RAM Monitor Timing ........................................................................................... 645
Figure 25.29 UBC Trigger Timing ............................................................................................. 646
Appendix D Package Dimensions
Figure D.1 FP-100M................................................................................................................... 703
Rev. 2.00, 09/04, page xxxiii of xl