SH7047 Datasheet, PDF (133/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

6.8 Data Transfer with Interrupt Request Signals
The following data transfers can be done using interrupt request signals:
• Activate DTC only, CPU interrupts according to DTC settings
The INTC masks CPU interrupts when the corresponding DTE bit is 1. The conditions for clearing
DTE and interrupt source flag are listed below.
DTE clear condition = DTC transfer end • DTECLR
Interrupt source flag clear condition = DTC transfer end • DTECLR
Where: DTECLR = DISEL + counter 0.
Figure 6.6 shows a control block diagram.
Interrupt source
Interrupt source
flag clear (by DTC)
DTER
DTE clear
CPU interrupt request
DTC activation
request
DTECLR
Transfer end
Figure 6.6 Interrupt Control Block Diagram
6.8.1
Handling Interrupt Request Signals as Sources for DTC Activating and CPU
Interrupt
1. For DTC, set the corresponding DTE bits and DISEL bits to 1.
2. Activating sources are applied to the DTC when interrupts occur.
3. When the DTC performs a data transfer, it clears the DTE bit to 0 and sends an interrupt
request to the CPU. The activating source is not cleared.
4. The CPU clears interrupt sources in the interrupt processing routine then confirms the transfer
counter value. When the transfer counter value is not 0, the CPU sets the DTE bit to 1 and
allows the next data transfer. If the transfer counter value = 0, the CPU performs the necessary
end processing in the interrupt processing routine.
Rev. 2.00, 09/04, page 93 of 720