SH7047 Datasheet, PDF (551/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W Description
7, 6 —
All 0
R
Reserved
These bits are always read as 0 and should only be
written with 0.
5
POE6M1 0
R/W POE6 Mode 1 and 0
4
POE6M0 0
R/W These bits select the input mode of the POE6 pin.
00: Request accepted at falling edge of POE6 input
01: POE6 input is sampled for low level 16 times every
Pφ/8 clock, and request is accepted when all samples
are low level
10: POE6 input is sampled for low level 16 times every
Pφ/16 clock, and request is accepted when all
samples are low level
11: POE6 input is sampled for low level 16 times every
Pφ/128 clock, and request is accepted when all
samples are low level
3
POE5M1 0
R/W POE5 Mode 1 and 0
2
POE5M0 0
R/W These bits select the input mode of the POE5 pin.
00: Request accepted at falling edge of POE5 input
01: POE5 input is sampled for low level 16 times every
Pφ/8 clock, and request is accepted when all samples
are low level
10: POE5 input is sampled for low level 16 times every
Pφ/16 clock, and request is accepted when all
samples are low level
11: POE5 input is sampled for low level 16 times every
Pφ/128 clock, and request is accepted when all
samples are low level
1
POE4M1 0
0
POE4M0 0
R/W POE4 Mode 1 and 0
R/W These bits select the input mode of the POE4 pin.
00: Request accepted at falling edge of POE4 input
01: POE4 input is sampled for low level 16 times every
Pφ/8 clock, and request is accepted when all samples
are low level
10: POE4 input is sampled for low level 16 times every
Pφ/16 clock, and request is accepted when all
samples are low level
11: POE4 input is sampled for low level 16 times every
Pφ/128 clock, and request is accepted when all
samples are low level
Note: * Only 0 can be written to clear the flag.
Rev. 2.00, 09/04, page 511 of 720