SH7047 Datasheet, PDF (548/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

TGRU
Td
PreviousTGRU
PreviousTGRU
Td
TGRU
2Td
2Td
Count-up
Count down
Figure 16.17 Writing into Timer General Registers (When One Cycle is Not Output)
Writing Operation into Timer Period Data Register (TPDR) and Timer Dead Time Data
Register (TDDR) When MMT is Operating:
• Do not revise TPDR register when MMT is operating. Always use a buffer-write operation
through TPBR register.
• Do not revise TDDR register once an operation of MMT is invoked. When TDDR is revised, a
wave may not be output for as much as 1 cycle (full count period of 16 bits in TDCNT),
because a value cannot be written into TDCNT, which is compared to a value set in TDDR.
16.8 Port Output Enable (POE)
The port output enable (POE) circuit enables the MMT's output pins (POUA, POUB, POVA,
POVB, POWA, and POWB) to be placed in the high-impedance state by varying the input to pins
POE4 to POE6. An interrupt can also be requested at the same time.
In addition, the MMT's output pins will also enter the high-impedance state in standby mode or
when the oscillator halts.
16.8.1 Features
The POE circuit has the following features:
• Falling edge, Pφ/8 × 16 times, Pφ/16 × 16 times, or Pφ/128 × 16 times low-level sampling can
be set for each of input pins POE4 to POE6.
• The MMT's output pins can be placed in the high-impedance state at the falling edge or low-
level sampling of pins POE4 to POE6.
• An interrupt can be generated by input level sampling.
Rev. 2.00, 09/04, page 508 of 720