SH7047 Datasheet, PDF (470/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.3.8 Transmit Wait Registers (TXPR1, TXPR0)
TXPR1 and TXPR0 are 16-bit registers that are used to set a transmit wait (CAN bus arbitration
wait) for transmit messages stored in mailboxes.
• TXPR1
Bit Bit Name
15 TXPR31
14 TXPR30
13 TXPR29
12 TXPR28
11 TXPR27
10 TXPR26
9
TXPR25
8
TXPR24
7
TXPR23
6
TXPR22
5
TXPR21
4
TXPR20
3
TXPR19
2
TXPR18
1
TXPR17
0
TXPR16
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Set a transmit wait (CAN bus arbitration wait) for the
corresponding mailboxes from 16 to 31. When TXPRn
(n = 16 to 31) is set to 1, the message in mailbox n
enters transmit wait state.
0: Transmit message in corresponding mailbox is in
idle state
1: Transmit message in corresponding mailbox is
waiting for transmit
[Clearing conditions]
• Completion of message transmission
• Completion of transmission abort
TXPR flags can be cleared only when the messages
are transmitted normally.
Notes: 1. 1 can be written only when the mailbox is
configured as a transmit mailbox.
2. Restrictions apply to the use of the
mailbox 31 for transmission. Carefully
read section 15.8, Usage Notes.
Rev. 2.00, 09/04, page 430 of 720