SH7047 Datasheet, PDF (501/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery
from software standby mode. As an HCAN2 interrupt is initiated immediately when interrupts are
enabled (in the state in which the interrupt mask register (IMR0) is cleared), IRR0 should be
cleared.
Hardware reset
MCR0 = 1 (automatic)
IRR0 = 1 (automatic)
GSR3 = 1 (automatic)
Initialization of HCAN2 module
Clear IRR0
HCAN2 port setting
BCR setting
MBC setting
Mailbox initialization
Message transmission method setting
: Settings by user
: Processing by hardware
Bit configuration mode
Period in which BCR, MBC, etc.,
are initialized
IMR setting (interrupt mask setting)
MBIMR setting (interrupt mask setting)
MB[x] setting (receive identifier setting)
LAFM setting (receive identifier mask setting)
Set BCR
MCR0 = 0
GSR3 = 0 &
11 recessive bits received?
No
Yes
CAN bus communication enabled
Figure 15.5 Hardware Reset Flowchart
Rev. 2.00, 09/04, page 461 of 720