SH7047 Datasheet, PDF (648/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

24.2.2 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that performs AUD software reset control and
enables/disables the access to the on-chip RAM.
Initial
Bit Bit Name Value R/W Description
7, 6 
All 1
R/W Reserved
These bits are always read as 1, and should always be
written with 1.
5 to 2 
All 0
R
Reserved
These bits are always read as 0, and should always be
written with 0.
1
AUDSRST 0
R/W AUD Software Reset
This bit controls the AUD reset by software. When 0 is
written to AUDSRST, AUD module shifts to power-on
reset state.
0: Shifts to AUD reset state.
1: Clears the AUD reset.
0
RAME
1
R/W RAM Enable
This bit enables/disables the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
When this bit is cleared to 0, the access to the on-chip
RAM is disabled. In this case, an undefined value is
returned when reading or fetching the data or
instruction from the on-chip RAM, and writing to the on-
chip RAM is ignored.
When RAME is cleared to 0 to disable the on-chip
RAM, an instruction to access the on-chip RAM should
not be set next to the instruction to write to SYSCR. If
such an instruction is set, normal access is not
guaranteed.
When RAME is set to 1 to enable the on-chip RAM, an
instruction to read SYSCR should be set next to the
instruction to write to SYSCR. If an instruction to access
the on-chip RAM is set next to the instruction to write to
SYSCR, normal access is not guaranteed.
Rev. 2.00, 09/04, page 608 of 720