SH7047 Datasheet, PDF (226/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.3.8 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4.
When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT
counter.
Initial
Bit Bit Name value R/W Description
7
CST4
0
R/W Counter Start 4 and 3
6
CST3
0
R/W These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the TIOC
pin designated for output, the counter stops but the TIOC
pin output compare output level is retained. If TIOR is
written to when the CST bit is cleared to 0, the pin output
level will be changed to the set initial output value.
0: TCNT_4 and TCNT_3 count operation is stopped
1: TCNT_4 and TCNT_3 performs count operation
5 to 3 
All 0 R
Reserved
These bits are always read as 0. Only 0 should be written to
these bits.
2
CST2
0
R/W Counter Start 2 to 0
1
CST1
0
R/W These bits select operation or stoppage for TCNT.
0
CST0
0
R/W If 0 is written to the CST bit during operation with the TIOC
pin designated for output, the counter stops but the TIOC
pin output compare output level is retained. If TIOR is
written to when the CST bit is cleared to 0, the pin output
level will be changed to the set initial output value.
0: TCNT_2 to TCNT_0 count operation is stopped
1: TCNT_2 to TCNT_0 performs count operation
Rev. 2.00, 09/04, page 186 of 720