SH7047 Datasheet, PDF (489/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Register
Name Bit
MBx[4], 13
MBx[5]
12
Bit Name
NMC
ATX
R/W Description
R/W New Message Control
When this bit is cleared to 0, the mailbox of which
the RXPR bit is already set does not store the new
message but maintains the old one and sets the
corresponding bit in UMSR. When this bit is set to 1,
the mailbox of which the RXPR bit is already set is
overwritten with the new message and sets the
corresponding bit in UMSR.
This bit executes the treatment for an unread
message also when the remote frame is received.
When the remote frame is received, corresponding
bits of RFPR (remote request register) and RXPR
(receive complete register) registers for the mailbox
are set. An unread message is treated according to
the settings of this bit and RXPR when the remote
frame is received.
R/W Automatic Transmission of Data Frame
When this bit is set to 1 and the mailbox receives a
remote frame, the corresponding TXPR is
automatically set and the current contents of the
message data is transmitted as a data frame.
The scheduling of transmission is still governed by
the CAN identifier.
In order to use this function, MBC[2:0] needs to be
set to 001.
When a transmission is performed by this function,
the data length code (DLC) to be used is the one
that has been received.
Rev. 2.00, 09/04, page 449 of 720