SH7047 Datasheet, PDF (161/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Activating
Source
Generator
Activating
Source
DTC Vector
Transfer
Address
DTE Bit Source
Transfer
Destination Priority
Reserved

H'00000438 to 


00000443
High
A/D converter ADI1
(CH1)
H'00000444 DTEE5 ADDR
Arbitrary*
Reserved

H'00000446 


SCI2
RXI_2
H'00000448 DTEE3 RDR_2
Arbitrary*
TXI_2
H'0000044A DTEE2 Arbitrary* TDR_2
SCI3
RXI_3
H'0000044C DTEE1 RDR_3
Arbitrary*
TXI_3
H'0000044E DTEE0 Arbitrary* TDR_3
SCI4
RXI_4
H'00000450 DTEF7 RDR_4
Arbitrary*
TXI_4
H'00000452 DTEF6 Arbitrary* TDR_4
MMT
TGN
H'00000454 DTEF5 Arbitrary* Arbitrary*
TGM
H'00000456 DTEF4 Arbitrary* Arbitrary*
Reserved

H'00000458 


HCAN2
RM1
H'0000045A DTEF2 Arbitrary* Arbitrary*
Reserved

H'0000045C to 


H'0000049F
Software
Write to
DTCSR
H'0400+

DTVEC[7:0]
Arbitrary* Arbitrary* Low
Note: * External memory, memory-mapped external devices, on-chip memory, on-chip
peripheral modules (excluding DTC)
8.3.3 DTC Operation
Register information is stored in an on-chip RAM. When activated, the DTC reads register
information in an on-chip RAM and transfers data. After the data transfer, it writes updated
register information back to the RAM.
Pre-storage of register information in the RAM makes it possible to transfer data over any required
number of channels. The transfer mode can be specified as normal, repeat, and block transfer
mode. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single
activation source (chain transfer).
The 32-bit DTSAR designates the DTC transfer source address and the 32-bit DTDAR designates
the transfer destination address. After each transfer, DTSAR and DTDAR are independently
incremented, decremented, or left fixed depending on its register information.
Rev. 2.00, 09/04, page 121 of 720