SH7047 Datasheet, PDF (118/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value
13
IRQ1ES1 0
12
IRQ1ES0 0
11
IRQ2ES1 0
10
IRQ2ES0 0
9
IRQ3ES1 0
8
IRQ3ES0 0
7 to 0 
All 0
R/W Description
R/W This bit sets the IRQ1 interrupt request edge
R/W ^{detection mode.}
00: Interrupt request is detected on falling edge of
IRQ1 input
01: Interrupt request is detected on rising edge of
IRQ1 input
10: Interrupt request is detected on both of falling and
rising edge of IRQ1 input
11: Cannot be set
R/W This bit sets the IRQ2 interrupt request edge
R/W ^{detection mode.}
00: Interrupt request is detected on falling edge of
IRQ2 input
01: Interrupt request is detected on rising edge of
IRQ2 input
10: Interrupt request is detected on both of falling and
rising edge of IRQ2 input
11: Cannot be set
R/W This bit sets the IRQ3 interrupt request edge
R/W ^{detection mode.}
00: Interrupt request is detected on falling edge of
IRQ3 input
01: Interrupt request is detected on rising edge of
IRQ3 input
10: Interrupt request is detected on both of falling and
rising edge of IRQ3 input
11: Cannot be set
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00, 09/04, page 78 of 720