SH7047 Datasheet, PDF (139/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W
Description
5
ID1
0
R/W
Instruction Fetch/Data Access Select1 and 0
4
ID0
0
R/W
These bits select whether to break on instruction fetch
and/or data access cycles.
00: No user break interrupt occurs
01: Break on instruction fetch cycles
10: Break on data access cycles
11: Break on both instruction fetch and data access
cycles
3
RW1
0
R/W
Read/Write Select 1 and 0
2
RW0
0
R/W
These bits select whether to break on read and/or write
cycles
00: No user break interrupt occurs
01: Break on read cycles
10: Break on write cycles
11: Break on both read and write cycles
1
SZ1
0
R/W
Operand Size Select 1 and 0*
0
SZ0
0
R/W
These bits select operand size as a break condition.
00: Operand size is not a break condition
01: Break on byte access
10: Break on word access
11: Break on longword access
Note: * When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are
considered to be accessed in word-size (even when there are instructions in on-chip
memory and two instruction fetches are performed simultaneously in one bus cycle).
Operand size is word for instructions or determined by the operand size specified for
the CPU/DTC data access. It is not determined by the bus width of the space being
accessed.
Rev. 2.00, 09/04, page 99 of 720