SH7047 Datasheet, PDF (595/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

19.4 Input/Output Pins
The flash memory is controlled by means of the pins shown in table 19.2.
Table 19.2 Pin Configuration
Pin Name
I/O
Function
RES
Input
Reset
FWP
Input
Flash program/erase protection by hardware
MD1
Input
Sets this LSI's operating mode
MD0
Input
Sets this LSI's operating mode
TxD3
(PA9)*
Output
Serial transmit data output
RxD3
(PA8)*
Input
Serial receive data input
Note: * In boot mode, PA8 and PA9 pins are used as SCI pins.
19.5 Register Descriptions
The flash memory has the following registers. For details on register addresses and register states
during each processing, see appendix A, Internal I/O Register.
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Erase block register 2 (EBR2)
• RAM emulation register (RAMER)
19.5.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, see section 19.8, Flash
Memory Programming/Erasing.
Rev. 2.00, 09/04, page 555 of 720