SH7047 Datasheet, PDF (94/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

4.2 Function for Detecting the Oscillator Halt
This CPG can detect a clock halt and automatically cause the timer pins to become high-
impedance when any system abnormality causes the oscillator to halt. That is, when a change of
EXTAL has not been detected, the high-current 12 pins (PE9/TIOC3B, PE11/TIOC3D,
PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT, PE16/PUOA/
UBCTRG*/A10, PE17/PVOA/WAIT/A11, PE18/PWOA/A12, PE19/PUOB/RxD4/ A13,
PE20/PVOB/TxD4/A14, PE21/PWOB/SCK4/A15) are set to high-impedance regardless of PFC
setting.
Even in standby mode, these 12 pins become high-impedance regardless of PFC setting. These
pins enter the normal state after standby mode is released. When abnormalities that halt the
oscillator occur except in standby mode, other LSI operations become undefined. In this case, LSI
operations, including these 12 pins, become undefined even when the oscillator operation starts
again.
Note: * For flash version only
Rev. 2.00, 09/04, page 54 of 720