SH7047 Datasheet, PDF (508/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

the mailbox empty interrupt bit (IMR8) in the interrupt mask register (IMR) are both
simultaneously set to enable interrupts, interrupts may be sent to the CPU.
However, a transmit wait message cannot be canceled at the following times:
• During internal arbitration or CAN bus arbitration
• During data frame or remote frame transmission
Figure 15.9 shows a flowchart for transmit message cancellation.
Message transmit wait TXPR setting
Set TXCR bit corresponding to
message to be canceled
: Settings by user
: Processing by hardware
Cancellation possible?
Yes
Message not sent
Clear TXCR and TXPR
ABACK = 1
IRR8 = 1
No
Completion of message transmission
TXACK = 1
Clear TXCR and TXPR
IRR8 = 1
IMR8 = 1?
Yes
No
Interrupt to CPU (SLE1)
Clear TXACK
Clear ABACK
Clear IRR8
End of transmission/transmission
cancellation
Figure 15.9 Transmit Message Cancellation Flowchart
Rev. 2.00, 09/04, page 468 of 720