SH7047 Datasheet, PDF (155/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

8.2.7 DTC Enable Registers (DTER)
DTER which is comprised of seven registers, DTEA to DTEF, is a register that specifies DTC
activation interrupt sources. The correspondence between interrupt sources and DTE bits is shown
in table 8.1.
Initial
Bit Bit Name Value R/W Description
7
DTE*7 0
R/W DTC Activation Enable 7 to 0
6
DTE*6 0
5
DTE*5 0
4
DTE*4 0
3
DTE*3 0
2
DTE*2 0
1
DTE*1 0
0
DTE*0 0
R/W Setting this bit to 1 specifies the corresponding interrupt
R/W
source to a DTC activation source.
R/W
[Clearing conditions]
R/W
• When the DISEL bit is 1 and the data transfer has
R/W
ended
R/W
• When the specified number of transfers have ended
R/W
• 0 is written to the bit to be cleared after 1 has been
read from the bit
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not ended.
[Setting condition]
1 is written to the bit to be set after a 0 has been read
from the bit
Note: * The last character of the DTC enable register’s name comes here.
Example: DTEB3 in DTEB, etc.
Rev. 2.00, 09/04, page 115 of 720