SH7047 Datasheet, PDF (529/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

16.3.3 Timer Status Register (MMT_TSR)
The timer status register (MMT_TSR) holds status flags. (In this section, the name of this register
is abbreviated to TSR hereafter.)
Initial
Bit Bit Name Value
R/W Description
7
TCFD
1
R
Count Direction Flag
Status flag that indicates the count direction of the TCNT
counter.
0: TCNT counts down
1: TCNT counts up
6 to 2 —
All 0
R
Reserved
These bits are always read as 0 and should only be
written with 0.
1
TGFN
0
R/(W)* Output Compare Flag N
Status flag that indicates a compare match between TCNT
and 2Td (Td: TDDR value).
[Setting condition]
• When TCNT = 2Td
[Clearing condition]
• When 0 is written to TGFN after reading TGFN = 1
0
TGFM
0
R/(W)* Output Compare Flag M
Status flag that indicates a compare match between TCNT
and the TPDR register.
[Setting condition]
• When TCNT = TPDR
[Clearing condition]
• When 0 is written to TGFM after reading TGFM = 1
Note: * Can only be written with 0 for flag clearing.
Rev. 2.00, 09/04, page 489 of 720