SH7047 Datasheet, PDF (467/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.3.6 Interrupt Mask Register (IMR)
IMR is a 16-bit register that enables interrupt requests caused by IRR interrupt flags.
Initial
Bit Bit Name Value R/W Description
15
IMR15
1
R/W Timer Compare Match Interrupt 1 Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR15) is enabled. When set to 1, OVR1 is masked.
14
IMR14
1
R/W Timer Compare Match Interrupt 0 Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR14) is enabled. When set to 1, OVR1 is masked.
13
IMR13
1
R/W Timer Overflow Interrupt Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR13) is enabled. When set to 1, OVR1 is masked.
12
IMR12
1
R/W Bus Operation Interrupt Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR12) is enabled. When set to 1, OVR1 is masked.
11, 10 
All 1 R
Reserved
These bits are always read as 1. The write value should
always be 1.
9
IMR9
1
R/W Unread Interrupt Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR9) is enabled. When set to 1, OVR1 is masked.
8
IMR8
1
R/W Mailbox Empty Interrupt Mask
When this bit is cleared to 0, SLE1 (interrupt request by
IRR8) is enabled. When set to 1, SLE1 is masked.
7
IMR7
1
R/W Overload Frame Interrupt Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR7) is enabled. When set to 1, OVR1 is masked.
6
IMR6
1
R/W Bus Off/Bus Off Recovery Interrupt Mask
When this bit is cleared to 0, ERS1 (interrupt request by
IRR6) is enabled. When set to 1, ERS1 is masked.
5
IMR5
1
R/W Error Passive Interrupt Mask
When this bit is cleared to 0, ERS1 (interrupt request by
IRR5) is enabled. When set to 1, ERS1 is masked.
4
IMR4
1
R/W Receive Error Warning Interrupt Mask
When this bit is cleared to 0, ERS1 (interrupt request by
IRR4) is enabled. When set to 1, ERS1 is masked.
Rev. 2.00, 09/04, page 427 of 720