SH7047 Datasheet, PDF (103/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

5.3 Address Errors
5.3.1 The Cause of Address Error Exception
Address errors occur when instructions are fetched or data is read or written, as shown in table 5.6.
Table 5.6 Bus Cycles and Address Errors
Bus Cycle
Type
Bus Master Bus Cycle Description
Address Errors
Instruction CPU
fetch
Instruction fetched from even address
Instruction fetched from odd address
None (normal)
Address error occurs
Instruction fetched from other than on-chip None (normal)
peripheral module space*
Instruction fetched from on-chip peripheral Address error occurs
module space*
Instruction fetched from external memory
space when in single chip mode
Address error occurs
Data
CPU, DTC, Word data accessed from even address
read/write or AUD
Word data accessed from odd address
None (normal)
Address error occurs
Longword data accessed from a longword
boundary
None (normal)
Longword data accessed from other than a Address error occurs
long-word boundary
Byte or word data accessed in on-chip
peripheral module space*
None (normal)
Longword data accessed in 16-bit on-chip
peripheral module space*
None (normal)
Longword data accessed in 8-bit on-chip
peripheral module space*
Address error occurs
External memory space accessed when in Address error occurs
single chip mode
Note: * See section 9, Bus State Controller (BSC) for more information on the on-chip
peripheral module space.
Rev. 2.00, 09/04, page 63 of 720