SH7047 Datasheet, PDF (423/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

13.3.2 A/D Control/Status Registers 0, 1 (ADCSR_0, ADCSR_1)
ADCSR for each module controls A/D conversion operations.
Initial
Bit Bit Name Value R/W
Description
7
ADF
0
R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified channels
in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DTC is activated by an ADI interrupt and
ADDR is read with the DISEL bit in DTMR of DTC = 0
6
ADIE
0
R/W A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
5
ADM1
0
R/W A/D Mode 1 and 0
4
ADM0
0
R/W Select the A/D conversion mode.
00: Single mode
01: 4-channel scan mode
10: 8-channel scan mode
11: Setting prohibited
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
3

1
R
Reserved
This bit is always read as 1, and should only be written
with 1.
2
CH2
0
R/W Channel Select 2 to 0
1
CH1
0
R/W Select analog input channels. See table 13.2.
0
CH0
0
R/W When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
Note: * Only 0 can be written to clear the flag.
Rev. 2.00, 09/04, page 383 of 720