SH7047 Datasheet, PDF (183/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

When the wait is specified by software using WCR1, the wait input WAIT signal from outside is
sampled. Figure 9.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when the T_w state shifts to the T₂ state. When using external
waits, use a WCR1 setting of 1 state or more in case of extending CS assertion, and 2 states or
more otherwise.
CK
Address
CS0
Read
RD
Data
Write
WRL
Data
WAIT
T1
TW
TW
TWo
T2
Figure 9.5 Wait State Timing of External Space Access (Two Software Wait States + WAIT
Signal Wait State)
Rev. 2.00, 09/04, page 143 of 720