SH7047 Datasheet, PDF (654/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Oscillator
CK
NMI input
NMIE bit
SSBY bit
LSI state ^Program
NMI
exception
Exception
execution state _handling service routine
Software
standby mode
Oscillation WDT NMI exception
start time setting time handling
Oscillation stabilization
time
Figure 24.2 NMI Timing in Software Standby Mode
24.3.3 Hardware Standby Mode
Transition to Hardware Standby Mode: When the HSTBY pin is driven low, a transition is
made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power consumption. As long as the specified voltage is supplied, on-chip
RAM data is retained.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the HSTBY pin low.
Do not change the state of the mode pins (MD3 to MD0) while the CPU is in hardware standby
mode.
Clearing Hardware Standby Mode: Hardware standby mode is cleared by means of the HSTBY
pin and the RES pin. When the HSTBY pin is driven high while the RES pin is low, the reset state
is set and clock oscillation is started. Ensure that the RES pin is held low until the clock
oscillation stabilizes. When the RES pin is then driven high, a transition is made to the program
execution state via the power-on reset exception handling state.
Hardware Standby Mode Timing: Figure 24.3 shows a transition-timing example to hardware
standby mode.
Rev. 2.00, 09/04, page 614 of 720