SH7047 Datasheet, PDF (379/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value
R/W Description
2
TEND
1
R
Transmit End
[Setting conditions]
• Power-on reset, hardware standby mode, or
software standby mode
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
writes data to TDR
1
MPB
0
R
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its previous
state is retained.
0
MPBT
0
R/W Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit value to be added to
the transmit data.
Note: * Only 0 can be written, for flag clearing.
Rev. 2.00, 09/04, page 339 of 720