SH7047 Datasheet, PDF (140/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

7.2.4 User Break Control Register (UBCR)
The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or
disables user break interrupts and (2) sets the pulse width of the UBCTRG signal output in the
event of a break condition match.
Bit
15 to 3
Bit Name

Initial
Value
All 0
2
CKS1
0
1
CKS0
0
0
UBID
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Clock Select 1 and 0
R/W These bits specify the pulse width of the UBCTRG
signal output in the event of a condition match.
00: UBCTRG pulse width is φ
01: UBCTRG pulse width is φ/4
10: UBCTRG pulse width is φ/8
11: UBCTRG pulse width is φ/16
Note: φ means internal clock
R/W User Break Disable
Enables or disables user break interrupt request
generation in the event of a user break condition
match.
0: User break interrupt request is enabled
1: User break interrupt request is disabled
Rev. 2.00, 09/04, page 100 of 720