SH7047 Datasheet, PDF (485/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

• UMSR0
Bit Bit Name
15 UMSR15
14 UMSR14
13 UMSR13
12 UMSR12
11 UMSR11
10 UMSR10
9
UMSR9
8
UMSR8
7
UMSR7
6
UMSR6
5
UMSR5
4
UMSR4
3
UMSR3
2
UMSR2
1
UMSR1
0
UMSR0
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Unread receive message is overwritten by a new
message
[Setting condition]
• When a new message is received before RXPR
is cleared
[Clearing condition]
• Writing 1
Note: Writing operation by the CPU is valid only for
clearing condition (writing 1) of set status.
15.3.16 Mailboxes (MB0 to MB31)
Mailboxes play a role as message buffers to transmit/receive CAN frames. Each mailbox is
comprised of four identical storage fields (message control, message data, timestamp, and local
acceptance filter mask (LAFM)). The 32 mailboxes are available for the HCAN2.
The following table shows the address map for the control, data, timestamp, and LAFM/TTT
addresses for each mailbox.
Notes: 1. Since mailboxes are in RAM, their initial values after a power-on are undefined. Be
sure to initialize them by writing 0 or 1.
2. Set the mailbox configuration (MBC) bits of unused mailboxes to B'111, and no access
is recommended.
3. Only word access can be used in message control, timestamp, LAFM field. Word/bytes
access can be used in message data area.
4. When a message is received in the mailbox where the LAFM is enabled, set ID
(including EXT-ID when it is enabled) will be overwritten to the ID (EXT-ID) values
of received messages.
Rev. 2.00, 09/04, page 445 of 720