SH7047 Datasheet, PDF (372/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

12.3 Register Descriptions
The SCI has the following registers for each channel. For details on register addresses and register
states during each processing, refer to appendix A, Internal I/O Register.
Channel 2
• Serial Mode Register_2 (SMR_2)
• Bit Rate Register_2 (BRR_2)
• Serial Control Register_2 (SCR_2)
• Transmit Data Register_2 (TDR_2)
• Serial Status Register_2 (SSR_2)
• Receive Data Register_2 (RDR_2)
• Serial Direction Control Register_2 (SDCR_2)
Channel 3
• Serial Mode Register_3 (SMR_3)
• Bit Rate Register_3 (BRR_3)
• Serial Control Register_3 (SCR_3)
• Transmit Data Register_3 (TDR_3)
• Serial Status Register_3 (SSR_3)
• Receive Data Register_3 (RDR_3)
• Serial Direction Control Register_3 (SDCR_3)
Channel 4
• Serial Mode Register_4 (SMR_4)
• Bit Rate Register_4 (BRR_4)
• Serial Control Register_4 (SCR_4)
• Transmit Data Register_4 (TDR_4)
• Serial Status Register_4 (SSR_4)
• Receive Data Register_4 (RDR_4)
• Serial Direction Control Register_4 (SDCR_4)
Rev. 2.00, 09/04, page 332 of 720