SH7047 Datasheet, PDF (175/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

9.2 Input/Output Pin
Table 9.1 shows the bus state controller pin configuration.
Table 9.1 Pin Configuration
Name
Address bus
Data bus
Chip select
Abbr.
I/O
A17 to A0 O
D7 to D0
I/O
CS0
O
Read
Lower write
RD
O
WRL
O
Wait
WAIT
I
Bus request
BREQ
I
Bus acknowledge BACK
O
Description
Address output
8-bit data bus
Chip select signal indicating the area being
accessed
Strobe that indicates the read cycle
Strobe that indicates a write cycle to the lower 8
bits (D7 to D0)
Wait state request signal
Bus release request input
Bus use enable output
9.3 Register Configuration
The BSC has four registers. For details on these register addresses and register states in each
processing states, refer to appendix A, Internal I/O Register.
These registers are used to control wait states, bus width, and interfaces with memories like ROM
and SRAM. All registers are 16 bits.
• Bus control register 1 (BCR1)
• Bus control register 2 (BCR2)
• Wait control register 1 (WCR1)
• RAM emulation register (RAMER)
Rev. 2.00, 09/04, page 135 of 720