SH7047 Datasheet, PDF (570/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Register Bit
Initial
Bit Name Value R/W
Description
PBCR1 11
PBCR2 7
PB3MD2 0
PB3MD1 0
R/W PB3 Mode
R/W Select the function of the PB3/IRQ1/POE1/TXD4 pin.
PBCR2 6
PB3MD0 0
R/W 000: PB3 I/O (port)
100: Setting prohibited
001: IRQ1 input (INTC) 101: Setting prohibited
010: POE1 input (port) 110: Setting prohibited
011: Setting prohibited 111: TXD4 output (SCI)
PBCR1 10
PBCR2 5
PB2MD2 0
PB2MD1 0
R/W PB2 Mode
R/W Select the function of the PB2/IRQ0/POE0/RXD4 pin.
PBCR2 4
PB2MD0 0
R/W 000: PB2 I/O (port)
100: Setting prohibited
001: IRQ0 input (INTC) 101: Setting prohibited
010: POE0 input (port) 110: Setting prohibited
011: Setting prohibited 111: RXD4 input (SCI)
PBCR1 9
PB1MD2 0
R/W PB1 Mode
PBCR2 3
PBCR2 2
PB1MD1 0
PB1MD0 0*²
R/W Select the function of the PB1/A17/HRXD1/SCK4 pin.
R/W 000: PB1 I/O (port)
100: Setting prohibited
001: A17 output (BSC)
101: Setting prohibited
010: Setting prohibited
110: Setting prohibited
011: HRxD1 input (HCAN2) 111: SCK4 I/O (SCI)
PBCR2 1
PBCR2 0
PB0MD1 0
PB0MD0 0*²
R/W PB0 Mode
R/W Select the function of the PB0/A16/HTxD1 pin.
00: PB0 I/O (port)
10: Setting prohibited
01: A16 output (BSC) 11: HTxD1 output (HCAN2)
Notes: 1. The initial value is 1 in the on-chip ROM enabled/disabled 8-bit external-expansion
mode.
2. The initial value is 1 in the on-chip ROM disabled 8-bit external-expansion mode.
17.1.5 Port D I/O Register L (PDIORL)
The port D I/O register L (PDIORL) is a 16-bit readable/writable register that is used to set the
pins on port D as inputs or outputs. Bits PD8IOR to PD0IOR correspond to pins PD8 to PD0
(names of multiplexed pins are here given as port names and pin numbers alone). PDIORL is
enabled when the port D pins are functioning as general-purpose inputs/outputs (PD8 to PD0) and
SCK2 pins are functioning as inputs/outputs of SCI. In other states, PDIORL is disabled.
A given pin on port D will be an output pin if the corresponding bit in PDIORL is set to 1, and an
input pin if the bit is cleared to 0.
Bits 15 to 9 of PDIORL are reserved. These bits are always read as 0 and should only be written
with 0.
Rev. 2.00, 09/04, page 530 of 720