SH7047 Datasheet, PDF (131/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

6.7 Interrupt Response Time
Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception processing starts and fetching of the first instruction of the
interrupt service routine begins. Figure 6.5 shows an example of the pipeline operation when an
IRQ interrupt is accepted.
Table 6.3 Interrupt Response Time
Number of States
Item
NMI, Peripheral
Module
IRQ
Remarks
DTC active judgment
0 or 1
1
1 state required for
interrupt signals for which
DTC activation is possible
Interrupt priority judgment 2
3
and comparison with SR
mask bits
Wait for completion of
sequence currently being
executed by CPU
X (≥ 0)
X (≥ 0)
The longest sequence is for
interrupt or address-error
exception processing (X =
4 + m1 + m2 + m3 + m4). If
an interrupt-masking
instruction follows,
however, the time may be
even longer.
Time from start of interrupt
exception processing until
fetch of first instruction of
exception service routine
starts
5 + m1 + m2 + m3
5 + m1 + m2 + m3
Performs the saving PC
and SR, and vector
address fetch.
Interrupt
response
time
Total: (7 or 8) + m1 +
m2 + m3+X
Minimum: 10
9 + m1 + m2 +
m3 + X
12
0.25 0.3 µs at 40 MHz
Maximum: 12 + 2 (m1 + m2 13 + 2 (m1 + m2 0.48 µs at 40 MHz*
+ m3) + m4
+ m3) + m4
Note: * 0.48 µs at 40 MHz is the value in the case that m1 = m2 = m3 = m4 = 1.
m1 to m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Rev. 2.00, 09/04, page 91 of 720