SH7047 Datasheet, PDF (547/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Pφ
Address
Write signal
Compare match
signal
Interrupt request
signal
Buffer register
Compare register
write cycle
T1 T2
Compare register
address
N
Compare register
N
Figure 16.16 Contention between Compare Register Write and Compare Match
Pay Attention to the Notices Below, When a Value is Written into the Timer General
Register U (TGRU), Timer General Register V (TGRV), Timer General Register W
(TGRW), and in Case of Written into Free Operation Address (*):
• In case of counting up: Do not write a value {Previous value of TGRU + Td} into TGRU.
• In case of counting down: Do not write a value {Previous value of TGRU - Td} into TGRU.
In the same manner to TGRV and TGRW. When a value {Previous value of TGRU + Td} is
written (in case of counting down {Previous value of TGRU - Td}), the output of PUOA/PUOB,
PVOA/PVOB, PWOA/PWOB (corresponding to U, V, W phase) may not be output for 1 cycle.
Figure 16.17 shows the error case. When writing into the buffer operation address, these notes are
not relevant.
Note: * When addresses, H'FFFF8A1C, H'FFFF8A2C, H'FFFF8A3C are used as register
address for TBRU, TBRV, TBRW, respectively.
Rev. 2.00, 09/04, page 507 of 720