SH7047 Datasheet, PDF (44/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Notes: *1 ASEBRKAK, DBGMD pins: F-ZTAT version only
*2 Modules for F-ZTAT version only
Figure 1.1 Block Diagram of SH7047
Rev. 2.00, 09/04, page 4 of 720
: Peripheral address bus (12 bits)
: Peripheral data bus (16 bits)
: Internal address bus (32 bits)
: Internal upper data bus (16 bits)
: Internal lower data bus (16 bits)
PD8/UBCTRG
PD7/D7/AUDSYNC
PD6/D6/AUDCK
PD5/D5/AUDMD
PD4/D4/AUDRST
PD3/D3/AUDATA3
PD2/D2/SCK2/AUDATA2
PD1/D1/TXD2/AUDATA1
PD0/D0/RXD2/AUDATA0
DBGMD^*1
ASEBRKAK^*1
Multifunction timer
pulse unit
A/D Watchdog
converter timer
Controller
area network 2
Serial communication
interface
(×3 channels)
Compare match
timer
(×2 channels)
Motor management
timer (×1 channel)
H-UDI^*2
AVss
AVss
AVcc
AVcc
Vss
Vss
Vss
Vss
Vss
Vcc
Vcc
Bus state controller
User
break*2
controller
Interrupt
controller
Vcc
Vcc
FWP
VcL
CPU
VcL
Data transfer
controller
PLLVss
PLLCAP
PLL
PLLVcL
XTAL
EXTAL
NMI
RAM
Flash ROM/
mask ROM
AUD^*2
MD0
MD1
MD2
MD3
RES
WDTOVF
HSTBY
1.2 Internal Block Diagram