SH7047 Datasheet, PDF (135/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Section 7 User Break Controller (UBC)
The user break controller (UBC) provides functions that make program debugging easier. By
setting break conditions in the UBC, a user break interrupt is generated according to the contents
of the bus cycle generated by the CPU or DTC. This function makes it easy to design an effective
self-monitoring debugger, and customers of the chip can easily debug their programs without
using a large in-circuit emulator.
7.1 Overview
• There are 5 types of break compare conditions as follows:
 Address
 CPU cycle or DTC cycle
 Instruction fetch or data access
 Read or write
 Operand size: longword/word/byte
• User break interrupt generated upon satisfying break conditions
• User break interrupt generated before an instruction is executed by selecting break in the CPU
instruction fetch.
• Satisfaction of a break condition can be output to the UBCTRG pin.
• Module standby mode can be set
Rev. 2.00, 09/04, page 95 of 720