SH7047 Datasheet, PDF (304/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.7.8 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 10.76 shows the timing in this case.
TGR read cycle
T1
T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
X
M
Internal data bus
M
Figure 10.76 Contention between TGR Read and Input Capture
Rev. 2.00, 09/04, page 264 of 720