SH7047 Datasheet, PDF (422/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

13.3 Register Description
The A/D converter has the following registers. For details on register addresses, refer to appendix
A, Internal I/O Register.
• A/D data register 0 (H/L) (ADDR0)
• A/D data register 1 (H/L) (ADDR1)
• A/D data register 2 (H/L) (ADDR2)
• A/D data register 3 (H/L) (ADDR3)
• A/D data register 4 (H/L) (ADDR4)
• A/D data register 5 (H/L) (ADDR5)
• A/D data register 6 (H/L) (ADDR6)
• A/D data register 7 (H/L) (ADDR7)
• A/D data register 8 (H/L) (ADDR8)
• A/D data register 9 (H/L) (ADDR9)
• A/D data register 10 (H/L) (ADDR10)
• A/D data register 11 (H/L) (ADDR11)
• A/D data register 12 (H/L) (ADDR12)
• A/D data register 13 (H/L) (ADDR13)
• A/D data register 14 (H/L) (ADDR14)
• A/D data register 15 (H/L) (ADDR15)
• A/D control/status register_0 (ADCSR_0)
• A/D control/status register_1 (ADCSR_1)
• A/D control register_0 (ADCR_0)
• A/D control register_1 (ADCR_1)
• A/D trigger select register (ADTSR)
13.3.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15)
ADDRs are 16-bit read-only registers. The conversion result for each analog input channel is
stored in ADDR with the corresponding number. (For example, the conversion result of AN4 is
stored in ADDR4.)
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading the ADDR, read the upper byte before the lower byte, or read in word unit. The
initial value of ADDR is H'0000.
Rev. 2.00, 09/04, page 382 of 720