SH7047 Datasheet, PDF (528/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

16.3.2 Timer Control Register (TCNR)
The timer control register (TCNR) controls the enabling or disabling of interrupt requests, selects
the enabling or disabling of register access, and selects counter operation or halting.
Initial
Bit Bit Name Value
7
TTGE
0
6
CST
0
5
RPRO
0
4 to 2 —
All 0
1
TGIEN
0
0
TGIEM
0
R/W Description
R/W A/D Start-Conversion request Enable
Enables or disables the generation of A/D start-conversion
requests when the TGFN or TGFM bit of the timer status
register (TSR) is set.
0: Disable request
1: Enable request
R/W Timer Counter Start
Selects operation or halting of the timer counter (TCNT)
and timer dead time counter (TDCNT).
0: TCNT and TDCNT operation is halted
1: TCNT and TDCNT perform count operations
R/W Register Protects
Enables or disables the reading of registers other than
TSR, and enables or disables the writing to registers other
than TBRU to TBRW, TPBR, and TSR. Writes to TCNR
itself are also disabled. Note that reset input is necessary
in order to write to these registers again.
0: Register access enabled
1: Register access disabled
R
Reserved
These bits are always read as 0. Only 0 should be written
to these bits.
R/W TGR Interrupt Enable N
Enables or disables interrupt requests by the TGFN bit
when TGFN is set to 1 in the TSR register.
0: Interrupt requests by TGFN bit disabled
1: Interrupt requests by TGFN bit enabled
R/W TGR Interrupt Enable M
Enables or disables interrupt requests by the TGFM bit
when TGFM is set to 1 in the TSR register.
0: Interrupt requests by TGFM bit disabled
1: Interrupt requests by TGFM bit enabled
Rev. 2.00, 09/04, page 488 of 720