SH7047 Datasheet, PDF (428/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

13.4.3 Single-Cycle Scan Mode
In single-cycle scan mode, A/D conversion is to be performed once on the specified channels
(eight channels maximum). Operations are as follows.
1. When the ADST bit in ADCR is set to 1 by a software, MTU, MMT, or external trigger input,
A/D conversion starts on the channel with the lowest number in the group (AN0, AN1, ...,
AN3).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter
enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D
conversion stops and the A/D converter enters the idle state.
13.4.4 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter
samples the analog input when the A/D conversion start delay time (t_D) has passed after the ADST
bit in ADCR is set to 1, then starts conversion. Figure 13.2 shows the A/D conversion timing.
Table 13.3 shows the A/D conversion time.
As indicated in figure 13.2, the A/D conversion time (t_CONV) includes t_D and the input sampling time
(t_SPL). The length of t_D varies depending on the timing of the write access to ADCR. The total
conversion time therefore varies within the ranges indicated in table 13.3.
In scan mode, the values given in table 13.3 apply to the first conversion time. The values given
in table 13.4 apply to the second and subsequent conversions.
Rev. 2.00, 09/04, page 388 of 720