SH7047 Datasheet, PDF (117/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value
5
IRQ2S
0
4
IRQ3S
0
3 to 0 
All 0
R/W Description
R/W IRQ2 Sense Select
This bit sets the IRQ2 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ2
input
1: Interrupt request is detected on edge of IRQ2 input
(edge direction is selected by ICR2)
R/W IRQ3 Sense Select
This bit sets the IRQ3 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ3
input
1: Interrupt request is detected on edge of IRQ3 input
(edge direction is selected by ICR2)
R
Reserved
These bits are always read as 0. The write value
should always be 0.
6.3.2 Interrupt Control Register 2 (ICR2)
ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins IRQ0
to IRQ3. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the
edge detection mode by the sense select bits of IRQ0 to IRQ 3 in Interrupt control register 1
(ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the
setting of ICR2 is ignored.
Initial
Bit Bit Name Value
15
IRQ0ES1 0
14
IRQ0ES0 0
R/W Description
R/W This bit sets the IRQ0 interrupt request edge
R/W ^{detection mode.}
00: Interrupt request is detected on falling edge of
IRQ0 input
01: Interrupt request is detected on rising edge of
IRQ0 input
10: Interrupt request is detected on both of falling and
rising edge of IRQ0 input
11: Cannot be set
Rev. 2.00, 09/04, page 77 of 720