82801DB Datasheet, PDF (98/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
The I/O portion of the DMA cycle generates a PCI I/O cycle to one of four I/O addresses
(Table 5-10). Note that these cycles must be qualified by an active GNT# signal to the requesting
device.
Table 5-10. DMA Cycle vs. I/O Address
DMA Cycle Type
Normal
Normal TC
Verify
Verify TC
DMA I/O Address
00h
04h
0C0h
0C4h
PCI Cycle Type
I/O Read/Write
I/O Read/Write
I/O Read
I/O Read
5.5.3
DMA Addresses
The memory portion of the cycle generates a PCI memory read or memory write bus cycle (its
address representing the selected memory). The I/O portion of the DMA cycle generates a PCI
I/O cycle to one of the four I/O addresses listed in Table 5-10.
5.5.4 DMA Data Generation
The data generated by PC/PCI devices on I/O reads when they have an active GNT# is on the lower
two bytes of the PCI AD bus. Table 5-11 lists the PCI pins that the data appears on for 8- and 16-bit
channels. Each I/O read results in one memory write, and each memory read results in one
I/O write. If the I/O device is 8 bit, the ICH4 performs an 8-bit memory write. The ICH4 does not
assemble the I/O read into a DWord for writing to memory. Similarly, the ICH4 does not
disassemble a DWord read from memory to the I/O device.
Table 5-11. PCI Data Bus vs. DMA I/O Port Size
PCI DMA I/O Port Size
Byte
Word
PCI Data Bus Connection
AD[7:0]
AD[15:0]
5.5.5 DMA Byte Enable Generation
The byte enables generated by the ICH4 on I/O reads and writes must correspond to the size of the
I/O device. Table 5-12 defines the byte enables asserted for 8- and 16-bit DMA cycles.
Table 5-12. DMA I/O Cycle Width vs. BE[3:0]#
BE[3:0]#
1110b
1100b
Description
8-bit DMA I/O Cycle: Channels 0-3
16-bit DMA I/O Cycle: Channels 5-7
NOTE: For verify cycles the value of the Byte Enables (BEs) is a “don’t care”.
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Intel^® 82801DB ICH4 Datasheet