82801DB Datasheet, PDF (70/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
Figure 5-3. NMI# Generation Logic
IOCHK From SERIRQ Logic
NMI_SC
[IOCHK_NMI_EN]
AND
NMI_SC
[IOCHK_NMI_STS]
NMI_SC
[PCI_SERR_EN]
D30:F0 SECSTS
[SSE]
AND
NMI_SC
[SERR#_NMI_STS]
D30:F0 PDSTS
OR
[SSE]
TCO1_STS
[HUBNMI_STS]
TCO1_CNT
OR
[NMI_NOW]
OR
Hub Interface Parity
Error Detected
D30:F0 CMD
[Parity Error Response]
AND
PCI Parity Error detected
during AC'97, IDE or USB
Master Cycle
D30:F0 PD_STS
[DPD]
D30:F0 BRIDGE_CNT
[Parity Error Response
Enable]
AND
OR
D30:F0 SECSTS
[DPD]
PCI Parity Error detected
during LPC or Legacy DMA
Master Cycle
D31:F0 PCICMD
[PER]
AND
NMI_EN
[NMI_EN]
D31:F0 PCISTA
[DPED]
AND
To NMI#
Output
and
Gating
Logic
5.1.5 Parity Error Detection
The ICH4 can detect and report different parity errors in the system. The ICH4 can be programmed
to cause an NMI (or SMI# if NMI is routed to SMI#) based on detecting a parity error. The
conceptual logic diagram in Figure 5-3 details all the parity errors that the ICH4 can detect, along
with their respective enable bits, status bits, and the results.
Note: If NMIs are enabled, and parity error checking on PCI is also enabled, then parity errors will cause
an NMI. Some operating systems will not attempt to recover from this NMI, since it considers the
detection of a PCI error to be a catastrophic event.
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Intel^® 82801DB ICH4 Datasheet