82801DB Datasheet, PDF (465/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.2.18 NOTIFY_DLOW—Notify Data Low Byte Register
Register Offset: 16h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#
Bit
Description
DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received during the Host
7:0 Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
13.2.19 NOTIFY_DHIGH—Notify Data High Byte Register
Register Offset: 17h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#
Bit
Description
DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received during the Host
7:0 Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
Intel^® 82801DB ICH4 Datasheet
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