82801DB Datasheet, PDF (275/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Hub Interface to PCI Bridge Registers (D30:F0)
Hub Interface to PCI Bridge Registers
(D30:F0)
8
The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the
ICH4 implements the buffering and control logic between PCI and the hub interface. The
arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must
decode the ranges for the hub interface. All register contents will be lost when core well power is
removed.
8.1
PCI Configuration Registers (D30:F0)
Note: Registers that are not shown should be treated as Reserved (see Section 6.2 for details).
.
Table 8-1. Hub Interface PCI Configuration Register Address Map (HUB-PCI—D30:F0) (Sheet 1
of 2)
Offset
00–01h
02–03h
04–05h
06–07h
08h
0Ah
0Bh
0Dh
0Eh
18h
19h
1Ah
1Bh
1Ch
1Dh
1E–1Fh
20–21h
22–23h
24–25h
26–27h
30–31h
32–33h
Mnemonic
Register Name
VID
Vendor ID
DID
Device ID
CMD
PCI Device Command Register
PD_STS
PCI Device Status Register
REVID
Revision ID
SCC
Sub Class Code
BCC
Base Class Code
PMLT
Primary Master Latency Timer
HEADTYP
Header Type
PBUS_NUM
Primary Bus Number
SBUS_NUM
Secondary Bus Number
SUB_BUS_NUM Subordinate Bus Number
SMLT
Secondary Master Latency Timer
IOBASE
IO Base Register
IOLIM
IO Limit Register
SECSTS
Secondary Status Register
MEMBASE
Memory Base
MEMLIM
Memory Limit
PREF_MEM_BASE Prefetchable Memory Base
PREF_MEM_MLT Prefetchable Memory Limit
IOBASE_HI
I/O Base Upper 16 Bits
IOLIMIT_HI
I/O Limit Upper 16 Bits
Default
8086h
244Eh
0001h
0080h
See Note
04h
06h
00h
01h
00h
00h
00h
00h
F0h
00h
0280h
FFF0h
0000h
0000h
0000h
0000h
0000h
Type
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W, RO
R/W, RO
R/WC, RO
R/W
R/W
RO
RO
RO
RO
Intel^® 82801DB ICH4 Datasheet
275