82801DB Datasheet, PDF (221/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.18.4 Interrupts / SMI#
The ICH4 SMBus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN
bit.
Table 5-91 and Table 5-92 specify how the various enable bits in the SMBus function control the
generation of the interrupt, Host and Slave SMI, and Wake internal signals. The rows in the tables
are additive, which means that if more than one row is true for a particular scenario then the Results
for all of the activated rows will occur.
Table 5-90. Enable for SMBALERT#
Event
INTREN (Host
Control I/O
Register, Offset
02h, Bit 0)
SMB_SMI_EN
(Host Configu-
ration Register,
D31:F3:Offset 40h,
Bit 1)
SMBALERT_DIS
(Slave Command I/O
Register, Offset 11h,
Bit 2)
Result
SMBALERT#
X
X
asserted low
(always
X
1
reported in
Host Status
Register, Bit 5)
1
0
X
Wake generated
0
Slave SMI# generated
(SMBUS_SMI_STS)
0
Interrupt generated
Table 5-91. Enables for SMBus Slave Write and SMBus Host Events
Event
INTREN (Host Control
I/O Register, Offset
02h, Bit 0)
SMB_SMI_EN (Host
Configuration
Register,
D31:F3:Offset 40h,
Bit1)
Event
Slave Write to Wake/
SMI# Command
X
Slave Write to
SMLINK_SLAVE_SMI
X
Command
0
Any combination of
Host Status Register
1
[4:1] asserted
1
Wake generated when asleep.
X
Slave SMI# generated when
awake (SMBUS_SMI_STS).
X
Slave SMI# generated when in
the S0 state (SMBUS_SMI_STS)
X
None
0
Interrupt generated
1
Host SMI# generated
Table 5-92. Enables for the Host Notify Command
HOST_NOTIFY_INTREN SMB_SMI_EN (Host
(Slave Control I/O
Configuration Register,
Register, Offset 11h, bit 0) D31:F3:Off40h, Bit 1)
HOST_NOTIFY_WKEN
(Slave Control I/O
Register, Offset 11h, bit 1)
Result
0
X
0
None
X
X
1
Wake generated
1
0
X
Interrupt generated
Slave SMI#
1
1
X
generated
(SMBUS_SMI_STS)
Intel^® 82801DB ICH4 Datasheet
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