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82801DB Datasheet, PDF (494/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4) | |||
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AC â97 Modem Controller Registers (D31:F6)
15.1.1
15.1.2
15.1.3
VIDâVendor Identification Register (ModemâD31:F6)
Address Offset:
Default Value:
Lockable:
00â01h
8086
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
15:0 Vendor Identification Value â RO.
Description
DIDâDevice Identification Register (ModemâD31:F6)
Address Offset:
Default Value:
Lockable:
02â03h
24C6h
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
15:0 Device Identification Value â RO.
Description
PCICMDâPCI Command Register (ModemâD31:F6)
Address Offset:
Default Value:
Lockable:
04â05h
0000h
No
Attribute:
Size:
Power Well:
R/W, RO
16 bits
Core
PCICMD is a 16-bit control register. Refer to the PCI 2.2 specification for complete details on each
bit.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved. Read 0.
Fast Back to Back Enable (FBE) â RO. Not implemented. Hardwired to 0.
SERR# Enable (SEN) â RO. Not implemented. Hardwired to 0.
Wait Cycle Control (WCC) â RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) â RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS) â RO. Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) â RO. Not implemented. Hardwired to 0.
Special Cycle Enable (SCE) â RO. Not implemented. Hardwired to 0.
Bus Master Enable (BME) â R/W. Controls standard PCI bus mastering capabilities.
0 = Disable
1 = Enable
Memory Space Enable (MSE) â RO. Hardwired to 0; AC â97 does not respond to memory
accesses.
I/O Space Enable (IOSE) âR /W. This bit controls access to the I/O space registers.
0 = Disable access. (default = 0).
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
programmed prior to setting this bit.
494
Intel® 82801DB ICH4 Datasheet
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