82801DB Datasheet, PDF (563/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Register Index
Table A-1. Intel^® ICH4 PCI Configuration Registers (Sheet 3 of 10)
Register Name
Prefetchable Memory Base
Prefetchable Memory Limit
I/O Base Upper 16 Bits
I/O Limit Upper 16 Bits
Interrupt Line
Bridge Control
Hub Interface 1 Command Control
Register
Secondary PCI Device Hiding Register
ICH4 Configuration Register
Multi-Transaction Timer
PCI Master Status
Error Command Register
Error Status Register
Offset
24–25h
26–27h
30–31h
32–33h
3Ch
3E–3Fh
40–43h
44–45h
50–51h
70h
82h
90h
92h
Datasheet Location
Section 8.1.19, “PREF_MEM_BASE—Prefetchable Memory Base
Register (HUB-PCI—D30:F0)” on page 8-283
Section 8.1.20, “PREF_MEM_MLT—Prefetchable Memory Limit Register
(HUB-PCI—D30:F0)” on page 8-284
Section 8.1.21, “IOBASE_HI—I/O Base Upper 16 Bits Register (HUB-
PCI—D30:F0)” on page 8-284
Section 8.1.22, “IOLIM_HI—I/O Limit Upper 16 Bits Register (HUB-PCI—
D30:F0)” on page 8-284
Section 8.1.23, “INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0)”
on page 8-284
Section 8.1.24, “BRIDGE_CNT—Bridge Control Register (HUB-PCI—
D30:F0)” on page 8-285
Section 8.1.25, “HI1_CMD—Hub Interface 1 Command Control Register
(HUB-PCI—D30:F0)” on page 8-286
Section 8.1.26, “DEVICE_HIDE—Secondary PCI Device Hiding Register
(HUB-PCI—D30:F0)” on page 8-287
Section 8.1.27, “CNF—ICH4 Configuration Register (HUB-PCI—D30:F0)”
on page 8-288
Section 8.1.28, “MTT—Multi-Transaction Timer Register (HUB-PCI—
D30:F0)” on page 8-288
Section 8.1.29, “PCI_MAST_STS—PCI Master Status Register (HUB-
PCI—D30:F0)” on page 8-289
Section 8.1.30, “ERR_CMD—Error Command Register (HUB-PCI—
D30:F0)” on page 8-289
Section 8.1.31, “ERR_STS—Error Status Register (HUB-PCI—D30:F0)”
on page 8-290
Vendor ID
Device ID
PCI Command Register
PCI Device Status Register
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Header Type
ACPI Base Address Register
00–01h
02–03h
04–05h
06–07h
08h
09h
0Ah
0Bh
0Eh
40–43h
LPC Bridge D31:F0
Section 9.1.1, “VID—Vendor ID Register (LPC I/F—D31:F0)” on
page 9-292
Section 9.1.2, “DID—Device ID Register (LPC I/F—D31:F0)” on
page 9-292
Section 9.1.3, “PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)”
on page 9-293
Section 9.1.4, “PCISTA—PCI Device Status (LPC I/F—D31:F0)” on
page 9-294
Section 9.1.5, “REVID—Revision ID Register (LPC I/F—D31:F0)” on
page 9-294
Section 9.1.6, “PI—Programming Interface (LPC I/F—D31:F0)” on
page 9-295
Section 9.1.7, “SCC—Sub-Class Code Register (LPC I/F—D31:F0)” on
page 9-295
Section 9.1.8, “BCC—Base-Class Code Register (LPC I/F—D31:F0)” on
page 9-295
Section 9.1.9, “HEADTYP—Header Type Register (LPC I/F—D31:F0)” on
page 9-295
Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on
page 9-296
Intel^® 82801DB ICH4 Datasheet
563