82801DB Datasheet, PDF (437/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

EHCI Controller Registers (D29:F7)
Bit
Description
Host Controller Reset (HCRESET)  R/W. This control bit used by software to reset the host
controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset
(i.e., RSMRST# assertion and PWROK deassertion on the ICH4).
0 = This bit is set to 0 by the Host controller when the reset process is complete. Software cannot
terminate the reset process early by writing a 0 to this bit.
1 = When software writes a 1 to this bit, the Host controller resets its internal pipelines, timers,
counters, state machines, etc. to their initial value. Any transaction currently in progress on
USB is immediately terminated. A USB reset is not driven on downstream ports.
1
All operational registers, including port registers and port state machines are set to their initial
values. Port ownership reverts to the companion host controller(s), with the side effects
described in the EHCI spec. Software must re-initialize the host controller in order to return the
host controller to an operational state.
Software should not set this bit to a 1 when the HCHalted bit in the EHCI_STS register is a 0.
Attempting to reset an actively running host controller will result in undefined behavior. This
reset me be used to leave EHCI port test modes.
NOTE: PCI Configuration registers and Host Controller Capability Registers are not effected by this
reset.
Run/Stop (RS)  R/W.
0 = Stop (Default)
1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule. The Host
controller continues execution as long as this bit is set. When this bit is set to 0, the Host
controller completes the current transaction on the USB and then halts. The HC Halted bit in the
status register indicates when the Host controller has finished the transaction and has entered
the stopped state.
NOTE: Software should not write a 1 to this field unless the host controller is in the Halted state
(i.e., HCHalted in the EHCI_STS register is a 1). The Halted bit is cleared immediately when
0
the Run bit is set.
The following table explains how the different combinations of Run and Halted should be interpreted:
Run/Stop Halted
Interpretation
0
0
Valid- in the process of halting
0
1
Valid- halted
1
0
Valid- running
1
1
Invalid- the HCHalted bit clears immediately.
Memory read cycles initiated by the EHC that receive any status other than Successful will result in
this bit being cleared.
NOTE: The Command Register indicates the command to be executed by the serial bus host controller. Writing
to the register causes a command to be executed.
Intel^® 82801DB ICH4 Datasheet
437