82801DB Datasheet, PDF (290/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.31
ERR_STS—Error Status Register (HUB-PCI—D30:F0)
Offset Address: 92h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bit
Core
This register records the cause of system errors in Device 30. The actual assertion of SERR# is
enabled via the PCI Command register.
Bit
Description
7:3 Reserved
SERR# Due to Received Target Abort (SERR_RTA) — R/W.
2
0 = Software clears this bit by writing a 1 to it.
1 = The Intel^® ICH4 sets this bit when the ICH4 receives a target abort. If SERR_EN, the ICH4 will
also generate an SERR# when SERR_RTA is set.
1:0 Reserved
290
Intel^® 82801DB ICH4 Datasheet